ZyXEL NSA3xx - eth0: link is not ready - patch

[osa]

Hi. If OFW halts NSA320 or NSA310S (and probably NSA325) it sets network interface into "wol" mode (which does not work properly for me)
To fix this issue we can do power_resume trick or patch mv643xx_eth.c
Patch works with wheezy 3.2 kernel and should work with newer kernels (it also adds downshift)

$this->bbcode_second_pass_code('', '--- a/drivers/net/ethernet/marvell/mv643xx_eth.c 2014-04-09 03:20:47.000000000 +0200
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c 2014-06-13 19:12:20.341329352 +0200
@@ -2777,6 +2777,23 @@
{
struct phy_device *phy = mp->phy;

+ int reg;
+
+ /*Leds link and activity */
+ phy_write(mp->phy, 22, 0x3);
+ reg = phy_read(mp->phy, 16);
+ reg &=~0xf;
+ reg |=0xf;
+ phy_write(mp->phy, 16, reg);
+ phy_write(mp->phy, 22, 0x0);
+
+ /* Enable downshift; 4-pin cable may plug into gigabit switch */
+ phy_write(mp->phy, 22, 0x0);
+ reg = phy_read(mp->phy, 16);
+ reg |=(1<<11);
+ phy_write(mp->phy, 16, reg);
+
+
phy_reset(mp);

phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
')

[WarheadsSE]

And what affect does this have on devices without WOL? Devices other than the NSA3xx line?

[osa]

OFW makes some fancy registry changes and MAC settings on halt (sorry, they are not related to WOL). This patch sets network led blinking on NSA320 and fixes "link not ready". It also fixes "link not ready" on NSA310S (but not led).
NSA325 has this code for network led
$this->bbcode_second_pass_code('', '#if defined(CONFIG_ZYXEL_NSA325)
/* Set LED[2] pin is tristate; for communicating with MCU */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),17,&reg);
reg &= ~(1 << 4);
reg |= (1 << 5);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),17,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
#endif') and it could be patched like this
$this->bbcode_second_pass_code('', '
/* Set LED[2] pin is tristate; for communicating with MCU */
phy_write(mp->phy, 22, 0x3);
reg = phy_read(mp->phy, 17);
reg &= ~(1 << 4);
reg |= (1 << 5);
phy_write(mp->phy, 17, reg);
phy_write(mp->phy, 22, 0x0);
')
We can omnit downshift part (is it supported by all kirkwood chips?). I don't have other boxes to test (i can try on B3 later)

[WarheadsSE]

Please see: https://github.com/archlinuxarm/PKGBUIL ... atch#L3474

So while I welcome that patch that might resolve parts of this, I'd like to point out that any machine specific fixups (such as the MCU) should be done via the appropriate PHY subsystem additions. The patch however, should be adaptable for the mainline kernel we're using (obv plus our patch) in regards to the WOL/link state.