[Help] Compiling Firefox 9.0.1 for/on Pogoplug (armv5)

[moonman]

Hello everybody,

Ran into this problem today trying to compile firefox 9.0.1 on my plug (since there isn't one in the repo)

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{standard input}: Assembler messages:
{standard input}:39: Error: selected processor does not support ARM mode `strd r4,r5,[r10,#24]'
{standard input}:74: Error: selected processor does not support ARM mode `ldrd r4,r5,[r10,#(4*6)]'
make[3]: *** [MethodJIT.o] Error 1
make[3]: Leaving directory `/mozilla-release/js/src'
make[2]: *** [libs_tier_js] Error 2
make[2]: Leaving directory `/mozilla-release'
make[1]: *** [tier_js] Error 2
make[1]: Leaving directory `/mozilla-release'
make: *** [default] Error 2


Any suggestions are appreciated!

[WarheadsSE]

It's not in the repo because the builds fail... kinda like that

Looks like Assembly.

http://infocenter.arm.com/help/index.js ... a4273.html

[moonman]

The article says the problem has been fixed in the latest arm toolchain. So we just wait until the fix comes to us? I wonder if cross-compiling will work.

[WarheadsSE]

We don't use RVCT soo...

[moonman]

We don't use RVCT soo...

Well, I understand that. I guess what I meant is that assembler developers need to consider RVCT changes.

[Kurlon]

So, the offending bits are in js/src/methodjit/MethodJIT.cpp

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asm (
".text\n"
FUNCTION_HEADER_EXTRA
".globl " SYMBOL_STRING(JaegerTrampolineReturn)   "\n"
SYMBOL_STRING(JaegerTrampolineReturn) ":"         "\n"
"   strd    r4, r5, [r10, #24]"             "\n" /* fp->rval type,data */

    /* Tidy up. */
"   mov     r0, sp"                         "\n"
"   blx  " SYMBOL_STRING_VMFRAME(PopActiveVMFrame) "\n"

    /* Skip past the parameters we pushed (such as cx and the like). */
"   add     sp, sp, #(4*7 + 4*6)"           "\n"

    /* Set a 'true' return value to indicate successful completion. */
"   mov     r0, #1"                         "\n"
"   pop     {r4-r11,pc}"                    "\n"
);

and

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asm (
".text\n"
FUNCTION_HEADER_EXTRA
".globl " SYMBOL_STRING(JaegerInterpolineScripted)  "\n"
SYMBOL_STRING(JaegerInterpolineScripted) ":"        "\n"
    /* The only difference between JaegerInterpoline and JaegerInpolineScripted
is that the
     * scripted variant has to walk up to the previous StackFrame first. */
"   ldr     r10, [r10, #(4*4)]"             "\n"    /* Load f->prev_ */
"   str     r10, [sp, #(4*7)]"              "\n"    /* Update f->regs->fp_ */
    /* Fall through into JaegerInterpoline. */

FUNCTION_HEADER_EXTRA
".globl " SYMBOL_STRING(JaegerInterpoline)  "\n"
SYMBOL_STRING(JaegerInterpoline) ":"        "\n"
"   mov     r3, sp"                         "\n"    /* f */
"   mov     r2, r0"                         "\n"    /* returnReg */
"   mov     r1, r5"                         "\n"    /* returnType */
"   mov     r0, r4"                         "\n"    /* returnData */
"   blx  " SYMBOL_STRING_RELOC(js_InternalInterpret) "\n"
"   cmp     r0, #0"                         "\n"
"   ldr     r10, [sp, #(4*7)]"              "\n"    /* Load (StackFrame*)f->regs
->fp_ */
"   ldrd    r4, r5, [r10, #(4*6)]"          "\n"    /* Load rval payload and typ
e. */
"   ldr     r1, [sp, #(4*3)]"               "\n"    /* Load scratch. */
"   it      ne"                             "\n"
"   bxne    r0"                             "\n"
    /* Tidy up, then return 0. */
"   mov     r0, sp"                         "\n"
"   blx  " SYMBOL_STRING_VMFRAME(PopActiveVMFrame) "\n"
"   add     sp, sp, #(4*7 + 4*6)"           "\n"
"   mov     r0, #0"                         "\n"
"   pop     {r4-r11,pc}"                    "\n"
);


Can those be replaced with two 32bit loads and stores? (I'm in way over my head, trying to remember ye olde HC11 code...)

[Kurlon]

Behold, ASM by google... if my bodgery is right...

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"   strd    r4, r5, [r10, #24]"             "\n" /* fp->rval type,data */

Store the contents of register r4 and r5 at address index in r10, offset 24bytes.

So, to replicate, we need to replace with two single register stores...

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"   str      r4, [r10, #24]"                 "\n" /* fp->rval type,data */
"   str      r5, [r10, #30]"                 "\n" /* Converted from single strd */

Do the same hack for the ldrd.

On the other hand the notes say ARMv5E should support STRD and LDRD so maybe whatever's being passed to the assembler on the command line is botching the cpu setting? Is FF targeting just ARMv5?

[WarheadsSE]

Ah, but not all SoC are alike... strd is a 64bit isnt it?

[Kurlon]

Yup, 64bits of data moved in one instruction.

[WarheadsSE]

Ok, trying a straight build (./configure, make) of the current beta on my GFN with the following patch:

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--- MethodJIT.cpp.orig   2012-01-24 18:27:17.000000000 -0500
+++ MethodJIT.cpp   2012-01-24 18:29:47.000000000 -0500
@@ -564,7 +564,8 @@ asm (
 FUNCTION_HEADER_EXTRA
 ".globl " SYMBOL_STRING(JaegerTrampolineReturn)   "\n"
 SYMBOL_STRING(JaegerTrampolineReturn) ":"         "\n"
-"   strd    r4, r5, [r10, #24]"             "\n" /* fp->rval type,data */
+"   str     r4, [r10, #24]"             "\n" /* fp->rval type,data */
+"   str     r5, [r10, #28]"             "\n" /* fp->rval type,data */
 
     /* Tidy up. */
 "   mov     r0, sp"                         "\n"
@@ -624,7 +625,8 @@ SYMBOL_STRING(JaegerInterpoline) ":"
 "   blx  " SYMBOL_STRING_RELOC(js_InternalInterpret) "\n"
 "   cmp     r0, #0"                         "\n"
 "   ldr     r10, [sp, #(4*7)]"              "\n"    /* Load (StackFrame*)f->regs->fp_ */
-"   ldrd    r4, r5, [r10, #(4*6)]"          "\n"    /* Load rval payload and type. */
+"   ldr     r4, [r10, #(4*6)]"          "\n"    /* Load rval payload and type. */
+"   ldr     r5, [r10, #((4*6)+4)]"          "\n"    /* Load rval payload and type. */
 "   ldr     r1, [sp, #(4*3)]"               "\n"    /* Load scratch. */
 "   it      ne"                             "\n"
 "   bxne    r0"                             "\n"


edit: Offsets tweaked as WarheadsSE caught a botched bit of math with my offsets.