Acer Chromebook CB5-311 mainline

[fedup]

I discovered that the write protection screw on acer 13 is labelled JP10, as mentioned earlier by DiskNoFun. In chromeos I checked the write protection status:
$ sudo flashrom --wp-status
The write protection was indeed disabled.
So I then tried to enable it with:
$ sudo flashrom --wp-enable
Rather to my suprise it was then enabled and I was unable to read from the spi. So I tried to disable write protection.
$ sudo flashrom --wp-disable
I was unable to do this so had to take the chromebook apart. I removed the JP10 screw and I was still unable to disable write protection. I had to scape of all the foil around the screw hole and after a couple of attempts was finally able to disable it!

So it seems that both reey's machine and mine were shipped without the write protection enabled. Possibly all the acer 13's were shipped like this under the Google radar. Theoretically the spi could have been flashed inadvertently.

[vman]

*Kernel 4.20.13 running*

After months of running 4.18, compiled in September last year, today I finally updated to the current Linux 4.20.

@reey, your linux-nyan PKGBUILD is working quite well!

So finally my Chromebook does use cpu frequency scaling:

$this->bbcode_second_pass_code('', '# cpupower frequency-info
analyzing CPU 0:
driver: cpufreq-dt
CPUs which run at the same hardware frequency: 0 1 2 3
CPUs which need to have their frequency coordinated by software: 0 1 2 3
maximum transition latency: 300 us
hardware limits: 204 MHz - 2.12 GHz
available frequency steps: 204 MHz, 306 MHz, 408 MHz, 510 MHz, 612 MHz, 714 MHz, 816 MHz, 918 MHz, 1.02 GHz, 1.12 GHz, 1.22 GHz, 1.33 GHz, 1.43 GHz, 1.53 GHz, 1.63 GHz, 1.73 GHz, 1.84 GHz, 1.94 GHz, 2.01 GHz, 2.12 GHz
available cpufreq governors: conservative userspace powersave ondemand performance schedutil
current policy: frequency should be within 204 MHz and 2.12 GHz.
The governor "ondemand" may decide which speed to use
within this range.
current CPU frequency: 1.43 GHz (asserted by call to hardware)')

My subjective impression is the computer does stay a little cooler now.

I'm having some trouble understanding all that is going on about U-Boot, and flashing the bootloader... but progress is good, it seems? So with Linux 5.1 in distributions, there is a chance we'd be able to use any ARM distribution without having to compile our own kernel? That's great news!

Also worth being aware of: from September 2019 on Google won't update Chrome OS on our devices anymore. From then on the advantages of actually running open source software will become more obvious...

[reey]

@fedup
I'm not sure, but shouldn't you also be able to read the SPI flash without disabling write protection, since it is just used for writing?

@vman
I'm happy, that someone is actually using it

Did anyone encounter any issues after enabling CPU frequency scaling?
On the mailing list they wrote, that it would be unsave to enable it..

What u-boot on the SPI flash would allow us to do is, that we would be able to use any prebuild image, which contains the nyan-big dtb for our device..
With u-boot chainloaded we would need to add the nyan-big u-boot to each prebuild image, if possible or need to create our own images..

It might even be possible, that all patches needed will be backported to kernel 4.19 so any image using these should be working then

Edit:
A way of entering tegrarcm from chromeOS would be great to allow others to flash u-boot on SPI without having to chainload u-boot beforehand..
Could someone who still has chromeOS on his device check if there is a command like "enterrcm" from u-boot also in chromeOS?

If not, could we just compile and run:
https://github.com/u-boot/u-boot/blob/m ... enterrcm.c
on linux?
I'm not an expert with C but it should be possible?
Only problem might be, that the compiler is missing on chromeOS..

[NoDiskNoFun]

@reey
vman is not the only one how uses your PKGBUILD.

I'm using cpufreq with OC to 2,3 GHz and i havn't any problems with that. I'm even able to play games like arx libertatis or openmw for hours without any crash.

If you provide the tegrarcm binary i'll try this for you

[fedup]

@reey
Just read my last post and and realised that I meant that I couldn't write to the SPI as I'd enabled write protection. I made a copy of the current coreboot once I'd removed the screw and disabled write protection. You're probably correct in saying that I would still have been able to read the SPI. I'm not going to enable write protection again to test it though!!
Still have not flashed the SPI.
Did you delete the chromeos partitions from the internal MMC?

As for cpufreq I've been running for a few months with it enabled, I prefer the conservative governor and have had no problems. The reason it was disabled was it caused a hang on resume caused by the DFLL clock speed being too low. I wonder if switching the governor to performance before a suspend would prevented this, It is now not possible to suspend to ram, it freezes in before sleep is achieved.
For now I've disabled suspend via:-
systemctl mask sleep.target suspend.target

At least now I can close the lid without a crash.

[reey]

Ok, so it seems like 5.0 allows us to drop a patch, but also adds a new one..
This patch:
https://github.com/torvalds/linux/commi ... d4542225ca
needs to be reverted for 5.0..
I'm not sure if nyan-big is the only device which has issues with that, since I'm pretty sure nvidia did some testing on jetson tk1 before they commited this..
If you stay with the old DTB from previous kernels you should be able to boot up anyway

I've already notified the mailing list and maybe we will see a fix for that soon

@fedup
yeah, I made a backup of the internal mmc, but It would take some time to restore it I think and before I do so, I would have to make another backup of my internal mmc which I'm using now for ubuntu..
Also I would have to open my chromebook again, to restore the spi flash..

It would be great if there was a way of booting chromeos from u-boot from an sd card or so..

@NoDiskNoFun
How could I forget, that you are using my PKGBUILD with overclocking?


What I also saw today, that on the Nintendo switch they just added the u-boot.elf file to the coreboot config and use that..
https://github.com/fail0verflow/switch- ... _defconfig

[NoDiskNoFun]

Did anyone tried to run i386 binaries with qemu-user-static? I tried archlinux32, debian und ubuntu, but i always get a segmantation fault if using pacman or apt. Compiling or using editors like nano does work nice but i rather would like to run wine on that. Anyone could hint me why i am getting segfaults when using a package manager? Is qemu-user-static that unstable? Some time ago i've seen a screenshot of someone running skyrim on a shield tablet but i dont know if he/she was using exagear or qemu. Also i've red that wine needs some kind of 3G/1G memory split compiled in kernel for Raspberry PI. Is this also a need for our devices and if yes, does this come with our kernel?

What i did:

install qemu-user static(AUR) and binfmt-support(AUR)
Install ArchLinux32 with a x86 machine on a usb stick
mount --bind all necessary filesystems (dev, proc, sys, etc/resolv.conf)
run chroot on usb stick

[fedup]

@reey
There is no enterrcm command on chromeos. I think the simplest way is to use flashrom from chromeos. However this has not been tested as at the moment.
I think the u-boot you flashed to your spi should work for all of us but I have not got a raspberry pi and spi clip if I end up with a brick. The legacy boot if it had worked would have been useful as the payload could be use to run enterrcm.
Have you tried installing your u-boot image that you copied from your spi, using flashrom to write back into the spi? Ideally it would be good if it was the same chromeos forked version of flashrom include with chromeos on the tegras. If that works if should be ok to do it from chromeos, I wonder if the write protection could be enabled afterwards to protect the SPI? Or is that only possible with coreboot?
I will probably flash the SPI with the tegra tools and chainloaded u-boot enterrcm method. Seems the safest way to me.

[mrala]

Hello, I as I understand the fix for the LPAE 4GB Ram was applied to 5.0, and wiil be backported to 4.19 ?
But 5.0 has that VIC patch that breaks boot, that in turn has a fix in the works kind of ?

I couldn't find the patch that fixed the "black/blank screen" issue. I know there were 2 (or 3) different patches for it.
Can you please point me to it ?

Cpe freq, was it disabled at some point for causing troubles ?
It is enabled by a DT change ?
What freqs it runs without it ?

I'll try dig harder. But if you can save me some digging by having this info at hand then Thank you.

[cbtech]

Dear all,
I am really haṕpy to have found this discussion and development! There seems to be a lot of development going on and helping to "free" our ACER Chromebook from in my opinion unneccessary restrictions.

I am ready to test new developments and also compile my own kernel if neccessary. What I may ask here is to have a short overview on the actual direction an setup as a starting point for further investigation.

My understanding is:

u-boot is running and supports the usage of 4GB on board DRAM?

u-boot from reey is meant to be flashed to partition 2 on the mmc?

u-boot may become the only bootloader on the Chromebook if flashed to SPI?

Kernel 4.2.20 is the latest stable Kernel from reey: do I need to sign the kernel after compilation?

I have flashed u-boot to mmcblk0p6, where my kernel should reside. u-boot starts, the /etxlinux on mmcblk0p7 is present and the PARTUUID corrected. With this set up, u-boot starts, but then I need to manually start the boot process. Is this meant to be so?

In short: I would like to have a short intro to better understand the actual emmc and spi setup (USB A to USB A cable ordered).

One remark: I have read all 16pages several times now, but I am missing some of the above information.
Having tested Kernel 4.2.20 direct boot from mmcblk0p6, u-boot from mmcblk0p6 with kernel in mmcblk0p7. As of now I obviously need my own kernel with TUN/TAP support for OpenVPN eg.

I don't want to be a consumer only, so if someone may give a hint or link were I should start to read before writing further silly questions, that would be great!

Thanks a lot!