by candlejack » Sun Aug 29, 2010 1:45 pm
erasing the NAND first: now that you mention it, that was my error. Oh that's probably how i bricked my uboot the first time, not erasing before a write
Well Yes i did get the CRC error on the parameters before using the saveenv to correct them.
As to the halt problem i had problems with your workaround but not without it.
$this->bbcode_second_pass_quote('', 'p')roc sheevaplug_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
...
from the dockstar.cfg
I think that says the jtag_reset utilizes nSRST, if so, as my cable had pin7 connected through the inverter to some reset-signal, that's why.
I googled some more on jtag and foung a good description on the wiggler, although in German
http://www.mikrocontroller.net/articles/JTAGin short:
$this->bbcode_second_pass_code('', '
DB25.2 -> INVERSE -> JTAG.15 (nSRST) -> DOCKSTAR 7
DB25.3 -> JTAG.7 (TMS) -> DOCKSTAR 4
DB25.4 -> JTAG.9 (TCK) -> DOCKSTAR 5
DB25.5 -> JTAG.5 (TDI) -> DOCKSTAR 3
DB25.6 -> JTAG.3 (TRST) -> shoud be DOCKSTAR 2 ( couldn't verify this )
DB25.11 <- JTAG.13 (TDO) <- DOCKSTAR 6
DB25.18-25 -> GND
DB25.8 <-> DB25.15 for use with ocdremote (OpenOCD or H-JTAG don't need it )
')
so much for using the first schematic to find and from there go by try and error, if i only knew this before.