Yes, this is the one I meant.
BTW, I just made an un-buffered "wiggler" with only 100 ohm resistors,
I changed "sheevaplug_int" to "dockstar_int" in "dockstar.cfg" with inverted SRST* bit:
proc dockstar_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
# jtag_reset 0 1 # open collector
jtag_reset 0 0 # non-inverter
feroceon.cpu arp_examine
halt 0
# jtag_reset 0 0 # open collector
jtag_reset 0 1 # non-inverter
wait_halt
It worked without pushing the reset button and I got the following:
Open On-Chip Debugger
> init
> dockstar_init
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0xffff0000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
> nand probe 0
NAND flash device 'NAND 256MiB 3,3V 8-bit' found
>