New Pink Pogoplug B04 bricked

[WarheadsSE]

If you could summarize, we'll put it into a guide.

[picco]

Hi WarheadsSE !
Very interesting topic!
So now i'm booting completly from sata drive. I reach 70 Mb/s with dd command, it rocks !

I made u-boot env variables permanent with saveenv command, now I can remove the serial connector
The only problem 'ive found is the slow frequency (600 Mhz).
Is it possible to post the stage1 binary with 800+ Mhz clock or at least to give informations about PLL registers addresses?
I own several omap boards , with the mw u-boot command it is very easy to set the clock .

Good job !

Occip

[WarheadsSE]

For the Oxnas line, the stage1 boot code sets the frequency, so I could generate a stage1 @ 800mhz for you, but give me a day or two, as I've been friggin swamped.

[WarheadsSE]

http://ppl.ug/Ze91Jqp1MEg/

Grab oxnas-sata-stage1.tgz, and READ the content of the write_stage1 script. You will need to point it to the correct device, as well as the stage1 you wish to use (I've included 700 & 850Mhz)

Oh yes, and for anyone thinking "I'll just over clock my nand oxnas!".. don't. I will call you an idiot, and laugh in your face. I am sorry to be mean, but for the love of $diety, if I had this packaged to overclock the NAND boot sequence, I WOULD SAY SO.

[picco]

Thanks WarheadsSE

Thanks for quick reply
I've tested the 850 Mhz stage1, it works very well.
I notice the system bus is the cpu clock divided by 2. At 850 Mhz the bus is at 425 Mhz. Maybe the ddr ram clock is too high at 925 MHz. Maybe it's possible to reach higher frequency by increasing ras/cas ram timing.

Thanks a lot

[WarheadsSE]

With the NDA (which is a pain to get), i have source access to the Stage1, so I'll have to have a look into that at some point, but I cannot say that it would be "safe" to make that modification. Thankfully, when booting from sata, it's an easy fix.

[picco]

Hi,

I'l trying to disassemble the binaries you provide. I saw that the frequency can be adjusted between 500 Mhz and 1 Ghz.
I would like to implement my own stage1 , but i've got problems with checksum ( at 0x48 offset). Maybe it's a crc32 (like u-boot header ) Any hints about this ?

(Maybe it's time to start a new topic ...)

Thanks

[WarheadsSE]

Listen,

The stage1 is under NDA from PLX, and it is their own code.

I cannot tell you that kind of information.

[kim]

$this->bbcode_second_pass_quote('redsquare', '
')
Missed off the file, try this:

https://rapidshare.com/files/4116281900/sata_update.tar.gz

[WarheadsSE]

I will put the needs together tonight, as I have what is needed.

I'll re-create it if I have to.