[ROCK64] Kernel doesn't work with eMMC after start

[mbakhterev]

Hello, world!

I'm trying to install ArchLinux ARM to the eMMC module in order to boot ROCK64 v2.0. I've completed the instructions, and the board starts, u-boot works, it boots kernel image and ramfs (though very slow, comparing to Bionic Linux, which i've also tried, and Bionic works). But then the kernel cannot read eMMC. I've collected some logs from Bionic successfull boot, from Android 9.0 successfull boot, and from ArchLinux unsuccessful boot. The logs can be loaded from here: http://k.imm.uran.ru/tmp/screenlog.tar.xz.

Some experts on MMC from the logs:

Bionic
$this->bbcode_second_pass_code('', 'board_init_sdmmc_pwr_en
booted from eMMC
Trying to boot from MMC1
MMC: rksdmmc@ff520000: 0, rksdmmc@ff500000: 1
mmc0(part 0) is current device
Scanning mmc 0:7...
[ 4.278946] dwmmc_rockchip ff520000.dwmmc: IDMAC supports 32-bit address mode.
[ 4.286163] dwmmc_rockchip ff520000.dwmmc: Using internal DMA controller.
[ 4.293219] dwmmc_rockchip ff520000.dwmmc: Version ID is 270a
[ 4.300124] dwmmc_rockchip ff520000.dwmmc: DW MMC controller at irq 42,32 bit host data width,256 deep fifo
[ 4.321238] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 4.342314] dwmmc_rockchip ff520000.dwmmc: 1 slots initialized
[ 4.354638] dwmmc_rockchip ff500000.dwmmc: IDMAC supports 32-bit address mode.
[ 4.366369] dwmmc_rockchip ff500000.dwmmc: Using internal DMA controller.
[ 4.377939] dwmmc_rockchip ff500000.dwmmc: Version ID is 270a
[ 4.389435] dwmmc_rockchip ff500000.dwmmc: DW MMC controller at irq 43,32 bit host data width,256 deep fifo
[ 4.413245] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 4.422362] mmc0: MAN_BKOPS_EN bit is not set
[ 4.433031] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[ 4.440708] dwmmc_rockchip ff500000.dwmmc: 1 slots initialized
[ 4.777281] dwmmc_rockchip ff520000.dwmmc: Successfully tuned phase to 130
[ 4.788948] mmc0: new HS200 MMC card at address 0001
[ 4.795315] mmcblk0: mmc0:0001 M8B16G 14.5 GiB
[ 4.801400] mmcblk0boot0: mmc0:0001 M8B16G partition 1 4.00 MiB
[ 4.807624] mmcblk0boot1: mmc0:0001 M8B16G partition 2 4.00 MiB
[ 4.814001] mmcblk0rpmb: mmc0:0001 M8B16G partition 3 4.00 MiB
[ 4.826491] mmcblk0: p1 p2 p3 p4 p5 p6 p7
[ 5.838858] EXT4-fs (mmcblk0p7): mounted filesystem with writeback data mode. Opts: (null)')

Android
$this->bbcode_second_pass_code('', 'mmc2:cmd19,100
SdmmcInit=2 0
SdmmcInit=0 NOT PRESENT
rksdmmc@ff500000: 1, rksdmmc@ff520000: 0
mmc_init: -95, time 9
mmc0(part 0) is current device
[ 0.962221] mmc1: MAN_BKOPS_EN bit is not set
[ 0.966062] mmc_host mmc1: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 1.231560] dwmmc_rockchip ff520000.dwmmc: Successfully tuned phase to 59
[ 1.231840] mmc1: new HS200 MMC card at address 0001
[ 1.232850] mmcblk1: mmc1:0001 M8B16G 14.5 GiB
[ 1.233344] mmcblk1boot0: mmc1:0001 M8B16G partition 1 4.00 MiB
[ 1.233785] mmcblk1boot1: mmc1:0001 M8B16G partition 2 4.00 MiB
[ 1.234247] mmcblk1rpmb: mmc1:0001 M8B16G partition 3 4.00 MiB
[ 1.238752] mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21')

Arch
$this->bbcode_second_pass_code('', 'SdmmcInit=2 0
SdmmcInit=0 2
MMC: rksdmmc@ff500000: 1, rksdmmc@ff520000: 0
Loading Environment from MMC... Card did not respond to voltage select!
mmc0(part 0) is current device
Scanning mmc 0:1...
[ 2.308634] sdmmc-regulator GPIO handle specifies active low - ignored
[ 5.361796] dwmmc_rockchip ff500000.dwmmc: IDMAC supports 32-bit address mode.
[ 5.362451] dwmmc_rockchip ff500000.dwmmc: Using internal DMA controller.
[ 5.363049] dwmmc_rockchip ff500000.dwmmc: Version ID is 270a
[ 5.363582] dwmmc_rockchip ff500000.dwmmc: DW MMC controller at irq 30,32 bit host data width,256 deep fifo
[ 5.375529] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 5.389424] dwmmc_rockchip ff520000.dwmmc: IDMAC supports 32-bit address mode.
[ 5.390073] dwmmc_rockchip ff520000.dwmmc: Using internal DMA controller.
[ 5.390678] dwmmc_rockchip ff520000.dwmmc: Version ID is 270a
[ 5.391227] dwmmc_rockchip ff520000.dwmmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo
[ 5.392699] mmc_host mmc1: card is non-removable.
[ 5.405616] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 5.506161] mmc_host mmc1: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[ 5.519143] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.519977] mmc1: new HS200 MMC card at address 0001
[ 5.521352] mmcblk1: mmc1:0001 M8B16G 14.5 GiB
[ 5.522333] mmcblk1boot0: mmc1:0001 M8B16G partition 1 4.00 MiB
[ 5.523436] mmcblk1boot1: mmc1:0001 M8B16G partition 2 4.00 MiB
[ 5.524127] mmcblk1rpmb: mmc1:0001 M8B16G partition 3 4.00 MiB, chardev (235:0)
[ 5.643216] mmcblk1: p1 p2 p3
[ 5.670155] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.683787] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.699757] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 5.750133] mmc_host mmc1: Bus speed (slot 0) = 200000000Hz (slot req 200000000Hz, actual 200000000HZ div = 0)
[ 5.764708] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.780067] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.780778] blk_update_request: I/O error, dev mmcblk1, sector 64 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[ 5.798095] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.
[ 5.798799] blk_update_request: I/O error, dev mmcblk1, sector 68 op 0x0:(READ) flags 0x80700 phys_seg 1 prio class 0
[ 5.813748] dwmmc_rockchip ff520000.dwmmc: All phases work, using default phase 0.')

So, it seems that the problem is with phase tuning (i don't know what it means, could anyone explain, please?). Can this be fixed with any kernel parameter?

Thanks for help in advance.

[summers]

Have you compared the device tree? That is usually where such things are set, but phasing is sometimes only available in bespoke drivers ...

Probably also worth reading the source code for the driver you seem to be using:

https://github.com/torvalds/linux/blob/ ... rockchip.c

You can see that there is only limited phasing, and not something the user can set. So probably the driver has been modified ...

[mbakhterev]

I've just compared device trees. They are different:

Bionic version
$this->bbcode_second_pass_code('', ' dwmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc\0rockchip,rk3288-dw-mshc";
reg = <0x00 0xff520000 0x00 0x4000>;
max-frequency = <0xbebc200>;
clocks = <0x02 0x13f 0x02 0x23 0x02 0x4c 0x02 0x50>;
clock-names = "biu\0ciu\0ciu-drv\0ciu-sample";
fifo-depth = <0x100>;
interrupts = <0x00 0x0e 0x04>;
status = "okay";
bus-width = <0x08>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
supports-emmc;
disable-wp;
num-slots = <0x01>;
pinctrl-names = "default";
pinctrl-0 = <0x72 0x73 0x74>;
vmmc-supply = <0x32>;
vqmmc-supply = <0x33>;
phandle = <0xc6>;
};
')

Arch version
$this->bbcode_second_pass_code('', 'dwmmc@ff520000 {
compatible = "rockchip,rk3328-dw-mshc\0rockchip,rk3288-dw-mshc";
reg = <0x00 0xff520000 0x00 0x4000>;
interrupts = <0x00 0x0e 0x04>;
clocks = <0x02 0x13f 0x02 0x23 0x02 0x4c 0x02 0x50>;
clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
fifo-depth = <0x100>;
status = "okay";
bus-width = <0x08>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <0x47 0x48 0x49>;
vmmc-supply = <0x19>;
vqmmc-supply = <0x1a>;
phandle = <0x93>;
};')

So... Is it safe to replace Arch version with Bionic one and try to boot?.. I've just tried. No effect, the kernel behaviour stays the same.

[mbakhterev]

Somehow i've hit this thread accidentatlly. https://forum.pine64.org/archive/index. ... -5258.html
The setting frequency limit to 150mhz helped. Android sets this limit too. But Bionic works with 200mhz max-frequency. So... The mystery is still unsolved.

[summers]

Yes can change the device tree, but as its mean to describe the hardware, and the hardware doesn't change, changes to the device tree should be rare, and I'd usually say just take the stock linux one. This said, the main kernel does have faults, si changes at times needed.

Assuming you are using a modern uboot, it can modify the device tree before boot. If you are changing thing like the memory speed, thats an easier way to do it. As much as anythiny if it goes wrong, you just pull the flash, an rewrite the /boot/boot.txt and correct the problem.

When I get home I'll dig out the commands to use ...

[summers]

OK easiest way to downclock the memory is to have uboot modify the device tree after loading.

Assuming you use /boot/boot.{txt,src} add a line like:

$this->bbcode_second_pass_code('', 'fdt addr ${fdt_addr_r}
fdt set /soc/apb@d0000000/mmc@74000 max-frequency <0x8f0d180>')

Do this after you've loaded the device tree into ram.

The above command is for odroid-c2 so you'll need to find where dwmmc@ff520000 is in the device tree. Easiest is to look under /proc/device-tree.

Not that although I've set speed above in hex, you can do it in decimal just as easily, which may make it easier if going for a round number.

Once booted with this, you can check it has worked by looking in /proc/device-tree.

[mbakhterev]

@summers, thanks for the detailed explanation! But, actually, the newest kernel package (5.6.3) has this frequency setting in the rk3328-rock64.dtb. After update system boots flawlessly. So, the next challenge is to fix the audio output. It seems there are suitable kernel drivers, but device-tree description is wrong.