by karog » Tue Mar 21, 2023 12:37 am
I have been running an N2 with arch for a few years now on kernel 6.2.7. This last Sat I got an N2+ and I am using the 12V 2A power supply from my N2 with a console UART cable. My boot fails very early booting from microSD or EMMC when I think it is testing DRAM. See
$this->bbcode_second_pass_code('', 'G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
no sdio debug board detected
L0:00000000
L1:00000703
L2:0000c067
L3:14000020
B2:00402000
B1:e0f83180
TE: 206202
BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13
Board ID = 5
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00036dae
DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09
board id: 5
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00030200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x0002c200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 255
Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : STREAM 0x003b0003 - 0x00000000 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
All ddr config failed...
')and then it repeats what I have already shown.
Woody, are you using a different u-boot.bin than comes with the latest download for this platform which is u-boot.bin size 854896 and I think dated 12-8-2019?
I am wondering if my hardware is bad. Curiously if I try to boot with SPI it begins with the same failure but instead of repeating the entire cycle it retries the DDRM check directly and succeeds. See:$this->bbcode_second_pass_code('', 'Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : STREAM 0x003b0003 - 0x00000000 0x00000000 0x00000000
INFO : STREAM 0x04020000 -
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
DDR4 probe
ddr clk to 1320MHz
Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SPI, src: 0x00020000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
')Notice that in the microSD/EMMC case, a few lines before the training is a line$this->bbcode_second_pass_code('', 'Cfg max: 1, cur: 1. Board id: 255. Force loop cfg')with max:1 cur: 1 whereas in the SPI case this line is$this->bbcode_second_pass_code('', 'Cfg max: 2, cur: 1. Board id: 255. Force loop cfg') with max: 2 and after the failure there is now the line$this->bbcode_second_pass_code('', 'Cfg max: 2, cur: 2. Board id: 255. Force loop cfg')with cur: 2 so in this SPI case it seems set to try twice unlike the first case and this second time succeeds.
I am not anywhere near loading the kernel or dtb or anything else from /boot. I have seen some remarks on the internet about beefier power supply but my 12v 2A should be way more than enough.
I also notice a bit before the DDR test, some lines that Load FIP HDR and Load ddrfw from the medium that contains the u-boot.bin like SD in the first case and SPI in the second case which is why I am wondering about u-boot.bin. But I have no real experience about this level of booting so I am seeking input.
Any thoughts that might help? Thx