Linux 2.6.28 Porting to Oxnas

[ftcodes]

The LED module was just a start

But you should have seen that they share a lot except the LED definition.

I made a common piece of code and specifics (LED tables), so it is actually not reinventing the stuff for every platform.

GMAC Eth driver:

I think the same about overhaul in general. However, that means to understand the whole linkage between SGDMA, SATA and Ethernet to get it cleaned up entirely.

It would be a good idea to reuse the PHY infrastructure of the kernel as well instead of that driver specific stuff with the PHY identifiers inside.

I did notice that topic with the never set interface speed too. But due to GBit connection on my side, I had no high priority for it yet.

[WarheadsSE]

Yes, we're just working on unifying all of that into simple a set of board files, instead of multiple essentially identical variations of the same module. Although modules do make it easier testing at bring-up.

I agree on the GMAC/PHY/MII interface. I had fixed the speed problem in the past, and get successful negotiations myself.

[ftcodes]

That is why I made it into modules but it is definitely possible to combine it. I saw that on the OpenWRT already but have not yet checked how they did it.

I integrated elazar's patch since I am using it for going further on those but first SGDMA relations have to be analyzed anyways to get real cleanup done.

[elazar]

$this->bbcode_second_pass_quote('ftcodes', 'T')he LED module was just a start

But you should have seen that they share a lot except the LED definition.

I made a common piece of code and specifics (LED tables), so it is actually not reinventing the stuff for every platform.

GMAC Eth driver:

I think the same about overhaul in general. However, that means to understand the whole linkage between SGDMA, SATA and Ethernet to get it cleaned up entirely.

It would be a good idea to reuse the PHY infrastructure of the kernel as well instead of that driver specific stuff with the PHY identifiers inside.

I did notice that topic with the never set interface speed too. But due to GBit connection on my side, I had no high priority for it yet.

[elazar]

Forgot a change in that patch, ready should be set back to 0.

elazar

[ftcodes]

elazar

Does that chip use the DMA controller for something else like SATA?

If not, a mere port would not work due to collisions with the SATA driver. It would require understanding the whole linkage. But still it is good to know where that IP core might be used too.

In fact those are sharing the same IP core. At least we can learn from it how it should be made right. However, the DMA stuff looks fairly different. At least we have a independent reference.
The PHY linkage looks different too.

[WarheadsSE]

$this->bbcode_second_pass_quote('elazar', 'F')orgot a change in that patch, ready should be set back to 0.

elazar

[elazar]

ftcodes:

I believe it does not: http://www.mjmwired.net/kernel/Document ... stmmac.txt

I am not that familiar with OXNAS particulars, what I understand from your post is that the SATA implementation shares the GMAC SGDMA controller? I guess in order to facilitate CE's SATA FastWrite feature?

elazar

[WarheadsSE]

It's not CE's but PLX's .. blech.

Figures. So we either code to like it, or leave it out and work around the resource contention...

$this->bbcode_second_pass_quote('WarheadsSE', '')$this->bbcode_second_pass_quote('elazar', 'F')orgot a change in that patch, ready should be set back to 0.

elazar