pxa270 sound issue

[bonjour]

Hi,

I'm trying to use the PXA270 modul (V2.2B) on an colibri evaluation board.

When I boot with Toradex Windows CE image (eboot eboot_3.9.bin and Windows CE image nk_ce5_3.9.bin), i don't have any problem with audio.

I can heard a sound which allow me to conclude that the colibri module, and evaluation board Audio Output are [OK].

But When i use Noser Linux image 2.6.35 with uboot, the detection of the audio controller failed.

I obtained this boot message:
pxa2xx_ac97_try_cold_reset: cold reset timeout (GSR=0x44)

I tried to read the developper's manual guide in order to find any mistakes in AC'97 controller driver.

I didn't find anything except the fact that before doing the cold reset, we need to switch off the AC link, and wait until the link is OK.

If i Had, this to the function pxa_ac97_cold_pxa27x, the AC'link never become OK!!


$this->bbcode_second_pass_code('', 'static inline void pxa_ac97_cold_pxa27x(void) /* sound/arm/pxa2xx-ac97-lib.c
{

unsigned long acoffd = 0;
unsigned long clk = 0;
unsigned long timeout = 100;



/* PXA27x Developers Manual Marvell April 2009 section 13.5.2.2.1
The following steps initiate a cold reset:*/


GCR |= GCR_ACLINK_OFF; /*1. Set GCR[ACOFF] bit to shutdown AC-link */
udelay(5);

while( !(acoffd) && (timeout--) ) /* 2. Wait for ACOFFD to be set in GSR[3] to ensure the link is cleanly shutdown*/
{
acoffd = GSR & GSR_ACOFFD ; /* Bit ACOFFD of register GSR is never set !!!!*/
udelay(50);
}

GCR &= GCR_COLD_RST; /*3. Mask the AC97 interrupt */
printk(KERN_INFO "GCR=%#lx",GCR);
GCR &= ~GCR_COLD_RST; /*4. Clear GCR[nCRST] to cold reset the AC97*/

udelay(5);

printk(KERN_INFO "GCR=%#lx",GCR); /*5. Read GCR to ensure split transaction is finished*/

clk_enable(ac97conf_clk); /*6. Set CKEN[31] to switch AC97_BITCLK to 13 MHz*/
udelay(5);

clk = CKEN; /*7. Read CKEN, which guarantees that the CKEN configuration occurred*/
if((!(clk & CKEN_31)) || (!(clk & CKEN_2)) )
printk(KERN_INFO "switch on AC97_BITCLK Failed");

GCR |= (GCR_CDONE_IE|GCR_SDONE_IE); /*8. Unmask AC97 interrupt*/

clk_disable(ac97conf_clk); /*9. Clear CKEN[31] to disable 13 MHz clock*/
udelay(5);

clk = CKEN; /*10. Read CKEN to guarantee that the CKEN configuration occurred*/

GCR = GCR_COLD_RST; /*11 Set GCR[nCRST] bit to pull AC97 out of reset*/
udelay(50);

GCR; /*12. Read GCR back to ensure the write to GCR happened*/

}
')

So, have you got any suggestion about this ?


thanks by advance

[WarheadsSE]

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