| Architecture: | aarch64 |
|---|---|
| Repository: | extra |
| Description: | The fastest free Verilog HDL simulator |
| Upstream URL: | https://www.veripool.org/verilator/ |
| License(s): | LGPL-3.0-only,Artistic-2.0 |
| Installed Size: | 36MiB |
| Build Date: | Sun Mar 15 14:52:43 2026 UTC |
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